SSE3

From Codex Gamicus
Jump to: navigation, search
SSE3
Basic Information
Type(s)
Terminology

SSE3, or Streaming SIMD Extensions 3, is an IA-32 SIMD instruction set, designed by Intel Corporation to rival AMD's 3DNow! instruction sets. SSE3 is the third iteration of the SSE SIMD instruction set, immediately preceded by SSE2. Intel introduced SSE3 in 2004 with the Pentium 4 processors that used the Prescott core. AMD introduced SSE3 in Revision E of their Athlon 64 processors, released in April 2005.

SSE3 adds thirteen new instructions to the processor, the most notable of which is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract horizontally in a register have been added. These instructions simplify the implementation of a number of DSP and 3D operations. SSE3 also includes new instructions related to HyperThreading.

These are the instructions added:

  • FISTTP
  • ADDSUBPS
  • ADDSUBPD
  • MOVSLDUP
  • MOVSHDUP
  • MOVDDUP
  • LDDQU
  • HADDPS
  • HSUBPS
  • HADDPD
  • HSUBPD
  • MONITOR
  • MWAIT